From October 28-29, the 10th (2022) China Semiconductor Equipment Annual Conference and Semiconductor Equipment and Core Components Exhibition (CSEAC), themed "Uniting Core Forces, Developing Core Equipment," was held at the Wuxi Taihu International Expo Center. At the event, Cai Dan, the Director of Test Operations at Moore Elite, gave a keynote speech on "Mass Production Testing and Mass Production Test Equipment in the Semiconductor Industry."

I. From R&D to Mass Production, Testing is a Key Essential Link

The semiconductor industry chain is very long. However, if viewed from the perspective of chip testing, the manufacturing process of chips can be divided into several stages, such as wafer manufacturing, wafer testing, chip packaging, and final product testing. Wafer testing is completed by combining ATE (Automatic Test Equipment) with Prober; final product testing is completed by combining ATE with Handler.

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Because the proportion of chip testing in the total manufacturing cost of chips is relatively small, usually in the range of a few percent, it is often overlooked by many chip design companies. However, in reality, chip testing is a key link in achieving the transition from R&D to mass production. First, we ensure the quality of the product through the dual processes of wafer testing and final product testing. Second, the quality of the test plan directly affects the yield and the size of the test cost.

Chip testing is a relatively complex task, involving many aspects such as test equipment, test procedures, test parameters, test conditions, test methodologies, new product mass production introduction processes and systems, verification of chip functions and performance, and test data analysis. To develop a high-quality test plan, developers need to be familiar with the functions of the chips being tested, the performance of the test equipment used, have a comprehensive semiconductor testing theory knowledge, and possess rich practical experience in mass production testing development.

II. The Goal of Engineering Operation PTE: Quick Introduction, Quality Improvement, and Cost Reduction

In the semiconductor industry, operations are generally divided into two major parts: engineering operation and manufacturing operation.

Engineering operation is also known as PTE (Product and Testing Engineering) in many companies.In engineering operations, our goals are very clear:

First, rapid market entry (time-to-market). This is particularly important for "consumer electronics". Missing the timing, a chip product may be eliminated by the market.

Second, improve quality. "Quality improvement" is a hurdle that the company cannot bypass to grow and become stronger. Domestic chip products are gradually moving from "low-end imitation" to "mid-to-high-end innovation", and the requirements for quality are getting higher and higher. With excellent quality to empower product value, the selling price and profit can far exceed the peers. From the three dimensions of product level, company level, and international perspective, the pursuit of excellent quality is the core competitiveness of the company in the long-term development.

Third, reduce costs. Although testing only accounts for a few percent of the total cost of the chip, if the quality of the test plan is not good, it can magnify the test cost several times or even dozens of times, becoming a heavy burden that operations cannot bear. In addition, for chip companies with large shipments, a saving of 1% or even 0.1% of the total cost is a huge sum of money.

The scope of engineering operations includes product engineering and test engineering.

The focus of product engineering is to improve yield, analyze defective products (including customer returns RMA), analyze costs, and think about how to reduce costs. The focus of test engineering is the development and implementation of test plans, including three main types of ATE test programs: QUAL programs for reliability testing, CHAR programs for chip verification, and CP and FT programs for mass production.

III. Different expectations for ATE test plans

First, the expectations for ATE test plans (QUAL) for reliability testing (Reliability Test)

First, quickly lock the inspection program (Lock test program ASAP). Before and after the chip reliability test, we need to use the ATE program to collect the drift of the chip's test results on key parameters. Some reliability test items have a long test time, and only by quickly locking the ATE QUAL test program can we start the reliability test, so as to know as soon as possible whether the chip's reliability design meets expectations.Second, adequate coverage ("Good-enough" test coverage). A program without sufficient coverage will lose the monitoring of test results for some key parameters of the chip, thereby neglecting potential quality risks.

Third, accuracy. We need a certain level of precision to track the drift of key parameters, and the test accuracy should be able to quantitatively reflect the changes in trends.

Fourth, stability (Gauge R&R - Repeatability & Reproducibility). Are the measurement results for the same parameter of the same chip consistent? Are the results consistent across different test platforms? Are the test results consistent when using different test fixtures on the same platform? Are the test results consistent across different positions on the same platform with the same fixture? These are the data we need to collect and analyze.

Next, expectations for the Characterization Test (CHAR) of the ATE test plan:

First, complete coverage (deliverable in phases). The CHAR test program is the largest and most comprehensive ATE test program in a project. Its function is to conduct the most complete detection of various IPs and parameters of the chip under different test conditions. The test results obtained by the CHAR program at different process corners, different voltages, and different temperatures help us to conduct a "comprehensive physical examination" of the chip, that is, characterization across "PVT".

Second, very accurate. Compared to the QUAL test program, we have higher expectations for the accuracy of the CHAR test results. Since the CHAR program is not used for mass production and is not very sensitive to test time, in order to more accurately analyze the performance of the chip, we can achieve the most accurate results within the capabilities of the ATE instrument by setting more precise measurement ranges, taking more sampling points for averaging, and reserving more wait time/settling time, etc.

Third, stability. Like the QUAL program, we also need stable ATE test results.

Finally, expectations for the Production Test (CP/FT) of the ATE test plan:

First, lowest cost. In any large-scale production, production cost is definitely our top priority. Therefore, we need to develop mass production test plans using "the most suitable, not the most expensive, and high-end ATE test equipment."

Second, very stable (High Gauge R&R). Among the three types of ATE test programs, the "mass production test program" has the highest requirement for stability. This is because the stability of the test results greatly affects the mass production yield, and the yield is also indirectly converted into the production cost of the chip, while also affecting the production capacity and delivery of the product.Thirdly, Sufficient Test Coverage. We opt for sufficient test coverage instead of complete coverage due to considerations of testing costs. It is common for the ATE CHAR program to take several minutes, dozens of minutes, or even several hours to complete the collection of test data for a single chip. Obviously, such a program cannot be used for mass production because it is too expensive! The hourly charge for a set of ATE testing equipment can range from about 10 US dollars to 200 US dollars. If a chip test requires dozens of minutes, then it must be sold at a sky-high price to break even. Therefore, we have to make trade-offs between test coverage and test time.

Fourth, Mass Production Testing is Defect-Oriented Testing, while Feature Verification is Specification-Oriented Testing.

A good product equals "good design" plus "good manufacturing". To verify whether it is a good design, we prove it through "feature verification testing". To verify whether it is good manufacturing, we prove it through "mass production testing". In semiconductor testing, we need to distinguish between mass production testing and feature verification testing. The characteristics of these two determine that we need to adopt different testing schemes in actual work. The testing costs of these two are also completely different.

For feature verification testing, we will select samples from multiple process lots of the chip to collect data, ensuring that the product parameters meet the requirements of the design technical specifications. The three common process lots are: FF/SS/TT (Fast-Fast/Slow-Slow/Typical-Typical), and complex ones can have up to 9 process lots.

For mass production testing, we need to ensure that there are no defects or outliers introduced in the production and manufacturing process. By comprehensively considering the expected parameters of the chip design, the results of the chip verification test, the statistical results of the small batch test, and the requirements of the client's product use, we formulate reasonable test limits. In addition, abnormal results near the test limit and far from the average value also need special attention. These outliers may be potential production and manufacturing defects.

Therefore, mass production testing is defect-oriented testing, while feature verification is specification-oriented testing.

For a product with a qualified design, the focus of mass production testing is to identify defects and outliers introduced in the manufacturing process at the lowest cost, quickly and reliably.

Fifth, How to Effectively Reduce the Cost of Semiconductor Mass Production Testing

The production test capability can be represented by the following formula:

Production Test Capability (UPH) = Number of DUTs passed the test / Time spent testing all DUTs (hours)The formula for calculating the test cost in production is as follows:

Test Cost = Cost per second of testing × Time spent testing all DUTs

Where, Cost per second of testing = (Dt + Dh + Cf + Cv) × ((Ttest + Tindex) / Ttest) × ((Tprod + Tdown + Tidle) / Tprod)

Dt: Depreciation of the test equipment (¥/second)

Dh: Depreciation of the handler or probe station (¥/second)

Cf: Fixed cost of the test site (¥/second)

Cv: Variable cost of the test site (¥/second)

Ttest: Test time (seconds)

Tindex: Indexing time (seconds)

Tprod: Average weekly production time of the test equipment (hours)Tdown: Average weekly downtime of the testing machine (hours)

Tidle: Average weekly idle time of the testing machine (hours)

After understanding the composition of chip testing costs, we can clearly see how to control and reduce mass production costs.

Firstly, the most direct method is to increase the number of chips that can be tested simultaneously per touch down by increasing the number of chips that can be tested at the same time.

In addition, using efficient testing techniques such as concurrent testing can also reduce the testing time per chip, but this requires certain demands on the DFT design of the chip.

Furthermore, by choosing the right testing equipment and optimizing the combination of testing equipment, that is, selecting "suitable, not the most expensive" equipment to meet performance and quality standards, the cost of testing per second can be reduced.

Again, by reasonably arranging the testing process and allocating testing items, the overall testing cost of the chip can be reduced. For example, generally speaking, the CP testing cost per chip is lower than FT. Therefore, under the premise of meeting quality and coverage (not involving defects introduced by the packaging process), placing the testing items in FT to CP testing can reduce the overall cost of the testing plan.

From the perspective of the testing factory, the following expectations are placed on the ATE equipment used for mass production of chips:

Firstly, the product coverage is extensive

A single model can cover multiple types of chips (Digital/Analog/Mixed-Sig/RF, etc.) to serve more customers; a single Configuration can cover multiple types of products, eliminating or reducing the workload of re-configuring the testing machine.Secondly, high stability

Hardware and software have few failures, with excellent MTBF/MTBA indicators; test results are accurate and stable, and will not cause low yield issues due to the test machine itself.

Thirdly, low cost of use

The price of the whole machine is reasonable; the price of spare parts and accessories is low; energy-saving and environmentally friendly, with low power consumption; the requirements for plant supporting facilities are simple, easy to install, maintain and repair; service costs are low, and technical service response is fast; license fees are low, and it is best to be free.

Fourthly, high degree of automation

High degree of automation, reducing the manual operation of operators/technicians; the machine is easy to operate, with a friendly UI interface; the equipment's software and hardware interface functions are complete and flexible, capable of quickly integrating with EAP (Equipment Automation Program) to achieve automated production and manufacturing; the hardware calibration of the test machine is highly automated; the software and hardware problem diagnosis tools are complete, capable of quickly and accurately identifying machine problems.

VI. Moore Elite Chip Automated Test Equipment (ATE), born for mass production

Moore Elite completed the acquisition of ATE equipment and R&D team from Texas Instruments TI in October 2020, established a wholly-owned subsidiary, and established a cross-national collaboration network with a Chinese R&D support team as the core, serving customers' chip testing and developing new generation equipment simultaneously. Moore Elite's ATE test equipment has undergone more than 20 years of time and mass production dual inspection, with experience in mass production testing of hundreds of billions of chips.

Since 2015, this series of ATE test machines have entered the supply chain of domestic mobile phone chip suppliers, testing products such as AP and PMIC, and have tested nearly a million wafers to date. In June 2021, the Moore Elite test team completed the qualification of a certain international RF SoC customer and began to enter mass production.

So far, the Moore Elite test team has completed the development of chip test solutions for dozens of customers in domestic and foreign fields and has entered mass production.In terms of product coverage, reliability, cost of use, and level of automation, Moore Elite's ATE equipment has significant advantages and is a very suitable model for mass production testing. Based on its own ATE platform, Moore Elite relies on a strong technical force and an experienced international team to provide customized test solutions for customers, helping them to reduce costs and increase efficiency.

At the beginning of 2022, Moore Elite completed the construction of the Wuxi Advanced Packaging and Testing Center, with a total area of 15,000 square meters. The factory's testing workshop is equipped with dozens of sets of CP/FT testing capacities based on the Moore Elite MEE-T series platform. From the beginning of the year to now, more than 30 chip products from 15 customers have completed engineering development in Moore Elite's Wuxi factory, and some products have been put into mass production.

In general, based on this series of testing platforms, Moore Elite adopts a trinity model of DFT design, self-organizing platforms, and test solutions to better serve the testing from R&D to mass production of chip products. Moore Elite's testing business attempts to solve the pain points of customers' chip products from R&D to mass production testing. The core is how to achieve collaborative innovation from design to testing to equipment, to make the most suitable plan, and thus achieve the most suitable effect and cost.