It can be observed that both the recent release of the MediaTek Tianji 9200 processor and Qualcomm's latest Snapdragon 8 Gen2 mobile platform seem to be standardizing the support for LPDDR5x memory at 8533Mbps. Currently, mobile phone manufacturers are fully engaged in the verification of LPDDR5x, with some already planning to launch projects supporting the full-blooded version of LPDDR5x at 8533Mbps by the end of this year.

The release of the new generation of flagship smartphone main chips indicates that the smartphone products will usher in a large-scale iteration from LPDDR5 to LPDDR5x. This will lead to performance improvements in mobile terminals, gaming, cameras, and AI applications, as well as the introduction of more new features, thereby further enhancing the user experience.

The foundation of this innovation stems from the upgrade and evolution of memory technology to LPDDR5X.

Looking back at the development history of LPDDR, LPDDR5X has ushered in new breakthroughs.

LPDDR, full name is Low Power Double Data Rate SDRAM, the full Chinese name is low power double channel synchronous dynamic random access memory. It is characterized by low power consumption and small size, usually stacked directly on top of the CPU processor with advanced packaging technology, and is the mainstream memory product for mobile application scenarios.

Advertisement

Since its birth more than ten years ago, this communication standard formulated by the American JEDEC Solid State Technology Association for low power memory has been upgraded and innovated with the evolution of technology and product demand.

From the first generation of LPDDR to the current LPDDR5X, each generation of LPDDR has doubled the internal read size and external transfer speed. There are also obvious generational differences in the application scenarios and customized requirements of LPDDR memory products.

LPDDR memory has evolved from DDR memory. Because the application scenarios of LPDDR are closer to DDR, there is a large intersection between the development process of LPDDR and DDR. LPDDR, which appeared in 2009, until LPDDR3 in 2013, can be said to have been following the footsteps of its elder brother. It is worth noting that by the time of LPDDR3, LPDDR3 began to be adopted by notebook platforms, including Mac Book Air, with its good performance and more excellent energy consumption ratio.

Subsequently, with the increasingly vigorous market and performance requirements of mobile platforms such as smartphones, LPDDR4 began to establish its own standard system according to its own application scenario requirements.

Starting from LPDDR4, it and DDR memory have taken different development paths.With the continuous growth of the mobile market, the demand for internal hardware speed and endurance indicators of products such as mobile phones is also increasing. The initial goal of LPDDR4 design was to increase the I/O interface data rate from 2133Mbps of LPDDR3 to 3200Mbps and even 4266Mbps. To achieve this goal, the JEDEC committee had to redesign the architecture of LPDDR, changing from a 16-bit single-channel chip to a 16-bit dual-channel chip per channel, with a total bit width of 32 bits.

The dual-channel architecture shortens the transmission distance of data signals from the memory array to the I/O paste chip. This reduces the power consumption required for a large amount of data transmission by the LPDDR4 interface. Moreover, the dual-channel architecture allows the clock and address buses to be placed together with the data bus. As a result, the skew between the data bus and the clock and address buses is minimized, enabling the LPDDR4 device to achieve a higher data rate.

In addition, LPDDR4 successfully broke through the original 8-bit prefetch to 16 bits, and its operating voltage was further reduced to 1.1V. Through a series of innovations such as changing the I/O interface signal transmission method and supporting power-saving functions under a wide range of frequencies, LPDDR4 has been highly successful in the mobile terminal, not only being commercialized before DDR4, but also widely welcomed by the mobile terminal market and rapidly popularized.

LPDDR5 has gone a step further. In February 2019, JEDEC officially released JESD209-5, the new low-power memory standard, Low Power Double Data Rate 5 (LPDDR5). Compared with the first-generation LPDDR4 standard released in 2014, the I/O speed of LPDDR5 has doubled to 6400 MT/s.

The JEDEC association believes that LPDDR5 is expected to greatly enhance the performance of the next generation of portable electronic devices. To achieve this improvement, the association standard has redesigned the LPDDR5 architecture, turning to a maximum of 16 Bank programmable and multi-clock architecture.

Based on the performance improvement of LPDDR5 technology, applications such as 4K high-definition live video on smartphones, the latest mobile games, and AI-based computational imaging all rely on higher memory bandwidth to provide a smoother experience. In the past two to three years, the penetration rate of LPDDR5 in the smartphone application has developed from less than 8% to nearly 40%, becoming an essential technology for the DRAM selection of the vast majority of smart flagship mobile phones.

Based on the performance foundation of LPDDR5, LPDDR5X has gone a step further, enabling a wider range of devices to have more AI and 5G-based functions.

According to relevant data, the power consumption of LPDDR5X memory has been greatly reduced in various scenarios, with short video power consumption reduced by 30%, long video power consumption reduced by 25%, and game power consumption reduced by 30%. Overall, the actual daily power consumption can be reduced by about 20%.

It is understood that compared with the full-blooded version of LPDDR5, the improvements brought by LPDDR5X mainly include three aspects: the data transfer rate has increased from 6400Mbps to 8533Mbps, with an increase of up to 33%; TX/RX balance improves signal integrity; and reliability can be improved through a new adaptive refresh management. Moreover, for mobile SoCs that support 8533Mbps LPDDR5X memory, the peak theoretical available bandwidth will further increase to 68.26GB/s.

In addition to performance improvements, in order to improve data transfer rates and the reliability of low-power memory subsystems, LPDDR5X has introduced a function called pre-emphasis to improve the signal-to-noise ratio and reduce bit error rates, as well as adaptive refresh management. In addition, there is a per-pin decision feedback equalizer, which can enhance the robustness of the memory channel. The pins of the two types of memory particles are fully compatible, which can simplify the memory control strategy required for the processor to support LPDDR5X from various aspects.In addition to this, LPDDR5X has been better optimized in terms of memory bank grouping and variable voltage, thereby effectively reducing the overall power consumption of the system.

Through cooperation and innovation in various aspects of the mobile ecosystem, the performance and power consumption of LPDDR5X will unlock the potential of new AI and 5G, such as operators building and investing in infrastructure, mobile phone manufacturers developing terminal devices that can utilize this new bandwidth, and the participation of the entire semiconductor industry.

Under market adversity, major memory manufacturers are still competing for layout.

Behind the normal iteration of LPDDR technology, under the demand for higher performance and capacity of smartphones, it is the fierce competition among the three memory giants, Samsung Electronics, SK Hynix, and Micron, in the latest technology field of global LPDDR5X.

From the perspective of market pattern, in the important storage chip segment of DRAM, Samsung, SK Hynix, and Micron are the well-deserved leaders. Data from the research institution ICInsights shows that the three major manufacturers accounted for 94% of the DRAM market in 2021. Among them, the first place, South Korea's Samsung Electronics, accounted for about 43.6%, the second place, South Korea's SK Hynix, accounted for about 27.7%, and the third place, the United States' Micron, accounted for about 22.8%.

According to ICinsights news reports, the weak economic situation and high inflation rate have slowed down the global demand for personal computers, mainstream smartphones, and other consumer electronic products.

As a result, the peak season for DRAM is not prosperous, and demand is spiraling down. It is expected that sales in the second half of 2022 will drop by 40% to $29.3 billion, and the DRAM market is expected to decline by 18% in 2022.

Samsung, SK Hynix, Micron, and other industry giants have all stated that quarterly memory sales have plummeted, and it is expected that the weak DRAM market will continue until the end of this year, at least until the first quarter of 2023.

As the storage chip market enters a downcycle, the industry becomes more and more conservative, such as reducing production capacity and flexibly adjusting capital expenditure. Micron Technology expects capital expenditure of $8 billion in the fiscal year 2023, a year-on-year decline of 33%; SK Hynix has decided to reduce the investment scale for next year from the expected 15-20 trillion won this year to more than 50%; in contrast, Samsung has not yet announced a reduction in investment for 2023, maintaining the tradition of counter-cyclical expansion, only indicating that it may flexibly adjust capital expenditure for equipment in 2023.

However, in adversity, major memory manufacturers have always maintained a positive attitude towards advanced technology investment.LPDDR5X has achieved higher bandwidth and faster speeds while reducing the overall power consumption of the system. In addition to the innovation in technical standards, the use of more advanced process nodes naturally leads to improved power efficiency.

For DRAM chips, advanced processes mean high energy efficiency, high capacity, and a better end-user experience. In terms of chip process technology, the current description of DRAM is different from before. Because the circuit structure is three-dimensional, linear measurement methods are no longer applicable. Instead of the previous nanometer scale, terms such as 1X, 1Y, 1Z, 1α, 1β, and 1γ have emerged to express the process.

Currently, DRAM advanced process technology has gone through four generations of 1x, 1y, 1z, and 1α. Samsung, SK Hynix, and Micron have entered the 1Xnm phase between 2016 and 2017, the 1Ynm phase between 2018 and 2019, and the 1Znm phase after 2020. The latest 1αnm is still in the 10+nm phase.

At present, major manufacturers are continuing to approach the 10nm scale.

SK Hynix: First to use HKMG process for LPDDR

On October 8, 2022, South Korea's SK Hynix took the lead and announced the start of sales of LPDDR5X (Low Power Double Data Rate 5X) mobile DRAM based on HKMG (High-K Metal Gate) technology.

Compared with the previous generation of chips, SK Hynix's new product is manufactured using the 1α process, with a 25% reduction in power consumption and a 33% increase in speed, achieving an operating speed of 8.5Gbps. It operates within the ultra-low voltage range of 1.01V to 1.12V set by the JEDEC Solid State Technology Association, ensuring the achievement of the industry's highest low-power standard.

In the DRAM industry, SK Hynix is the first to use the HKMG process for mobile DRAM.

With HKMG, a thin layer of high-k film can replace the existing SiON gate oxide layer in the transistor gate, reducing leakage current and improving chip reliability.In addition, by reducing the gate thickness, transistor miniaturization can be achieved, and the speed characteristics of transistors based on polycrystalline silicon/SiON can be improved.

SK Hynix has utilized the HKMG process to enhance performance while reducing power consumption, achieving a dual benefit and realizing active scaling and high efficiency.

Furthermore, on October 23, 2022, SK Hynix ordered the next-generation extreme ultraviolet (EUV) lithography machine with a high numerical aperture (0.55) from the lithography giant ASML, preparing for a significant undertaking. The EUV lithography machine will bring a more simplified process flow, and costs will continue to decrease as the process is further perfected.

It should be noted that, despite the use of EUV lithography machines, the LPDDR5X mobile DRAM based on HKMG technology announced by SK Hynix still belongs to the 1α node.

Samsung Electronics: Industry's fastest speed verified by Qualcomm

Following closely, on October 18, Samsung Electronics announced that its latest LPDDR5X DRAM, in cooperation with Qualcomm, has been verified at an industry-leading speed of 8.5Gbps.

It is understood that Samsung LPDDR5X adopts a 14nm process, achieving a significant increase in speed, capacity, and power consumption. Compared with the previous generation product LPDDR5, its operating speed has increased to 1.3 times, and power consumption has also been reduced by about 20%.

After optimization in cooperation with Qualcomm, the speed of LPDDR5X is stabilized at 7.5Gbps, which is still 1.2 times the speed of existing products. It is expected to be used in the next generation of smartphones to enhance the performance experience in ultra-high-resolution video recording and image recognition.

Samsung stated that the LPDDR5X memory has the advantages of low power consumption and high performance. It can not only be used in mobile phones but also has a wide range of applications in PCs, servers, and automobiles.At the Samsung Foundry Forum 2022 event held in October, Samsung also publicly disclosed its DRAM technology roadmap. According to the plan, Samsung will enter the 1β nm process phase in 2023, which is the fifth generation of 10nm-class DRAM products. To overcome the challenges of DRAM scaling beyond the 10nm range, Samsung has been developing disruptive solutions in patterning, materials, and architecture, with technologies such as high-K materials progressing smoothly.

Micron Technology: First to Launch 1β Node Process

On November 2, Micron officially launched its 1β node DRAM products and has already started sampling and testing with smartphone and chip platform partners. According to Micron, the 1β node DRAM products are now ready for mass production and will first adopt this new process technology in LPDDR5X mobile memory, with the highest speed reaching 8.5Gb/s.

It is reported that compared to 1α, the 1β technology can improve energy efficiency by about 15%, increase memory density by more than 35%, and the capacity of a single bare die can reach up to 16Gb. Micron believes that with the sampling of LPDDR5X, the mobile ecosystem will be the first to benefit from the advantages of 1β DRAM products, thereby unlocking the next generation of mobile innovation and advanced smartphone experiences while reducing power consumption.

As the world's most advanced DRAM process node, 1β represents an enhancement of Micron's leading position in the market and is closely connected to the mass shipment of the 1α technology node.

On the other hand, Micron is challenging the laws of physics through precise lithography and nano-manufacturing.

The scale of DRAM largely depends on the ability to provide more and faster memory per square millimeter of semiconductor area, which requires the miniaturization of circuits. However, as chips become smaller, defining circuit patterns on the chip requires challenging the laws of physics.

Although memory chips have begun to turn to a new tool that uses EUV lithography to overcome these technical challenges, Micron has bypassed this emerging technology by leveraging its proven cutting-edge nano-manufacturing and lithography techniques.

Micron stated that EUV technology is still in its early stages of development, and to avoid technical risks, Micron has adopted mature cutting-edge nano-manufacturing and lithography technology for the production of 1β. To achieve this, it is necessary to apply the company's proprietary advanced multi-patterning technology and immersion capabilities, such as proprietary advanced multiple exposure techniques and immersion lithography technology, to etch these tiny features with the highest precision.The greater capacity brought by this innovation will also enable smaller devices such as smartphones and IoT devices to accommodate more memory in compact spaces. High-density, low-power memory manufactured on 1β can achieve more efficient data flow between data-intensive smart things, systems, and applications, and enable more intelligence from the edge to the cloud. In the coming year, Micron will begin to expand its 1β portfolio in embedded, data center, client, consumer, industrial, and automotive fields.

In conclusion, although storage chips are facing a "collapse" in market prices, the long-term market confidence represented by the three giants still stands firm. Against this backdrop, continuously advancing the innovation of 1α, 1β, and 1γ processes will be the unchanging strategy of memory giants, and the technological competition in the storage chip track is still very fierce.

Whether it is the fifth-generation 10nm-class DRAM technology or the higher-layer stacked NAND Flash, storage giants are actively striving to maintain a leading position in the market and meet the market's demand for high-capacity, high-performance products, showing the potential for continuous development.

At the same time, the scope of future LPDDR use will also gradually expand from smartphones to AI, automotive, and data center applications, and the market prospects are becoming broader and broader.